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www.siliconstandard.com 1 of 16 two remote temperature sensors with smbus serial interface and system reset features description two channels: measures both remote and local t emperatures no calibration required smbus 2-wire serial interface programmable under/over-temperature alarms smbus alert response supported accuracy: 1c (+60c to +100c, remote) 3c (+60c to + 100c, local) average supply current during conversion of 320 a (typ) supply range of +3v to +5.5v small 8-lead so package applications desktop and notebook central office computers telecom equipme nt smart battery packs test and measurement lan servers multi - chip modules industrial controllers packing type tr: tape and reel ss8017xx example: SS8017TR ss8017 shipped in tape and reel ordering information the ss8017 contains a precise digital thermometer, a system-reset circuit, and a programmable thermal shutdown signal. the thermometer reports the temperature of two re- mote sensors. the remote sensors are d i- ode-connected transistors , typically a low-cost, eas ily mounted 2n3904 npn type which replaces conve n- tional thermistors or thermocouples. remote accuracy is 5c for multiple transistor manufacturers, with no calibration needed. the remote channel can also measure the die temperature of other ics, such as mi- croprocessors, that contain an on-chip, d i- ode-connected transistor. the 2-wire serial interface accepts standard system management bus (smbus tm ) write byte, read byte, send byte, and receive byte commands to program the alarm thresholds and to read temperature data. the data format is 7 bits plus sign, with each bit corre- sponding to 1c, in two?s-complement format. meas- urements can be done automatically and autono- mously, with the conve rsion rate programmed by the user or programmed to operate in a single-shot mode. the adjustable rate a llows the user to control the supply-current drain. ss8017 re v . 2.01 6/06 /200 3
www.siliconstandard.com 2 of 16 the ss8017 also contains a microprocessor ( p)su- pervisory circuit used to monitor the power supplies in p and digital systems. th is provides excellent circuit reliability and low cost by eliminating external compo- nents and adjustments when used with 5v -powered circuits. this circuit asserts a reset signal whenever the v cc supply voltage declines below a preset thres h- old, keeping it asserted for at least 140ms after v cc has risen above the reset threshold. the ss8 017 has an a ctive -low reset output. the reset comparator is designed to ignore fast transients on v cc . reset thres hold of this circuit is set to 4.38v. when the temperature of dx1 reaches or exceeds the tcrit1 (smbus 35h) threshold consecu tively for the number of times equal to the number of faults of the fq_th_shut registers, th_shut pin becomes logic high. the same mechanism is d uplicated for dx2. therefore, if either dx1 or dx2 continuously exceeds their respective tcrit, the th_shut will a ssert logic high to indicate a thermal shutdown event. the ss8017?s smbus device address is fixed to be 7ah for write and 7bh for read. the ss8017 is available in a small, 16-pin ssop su r- face -mount package. typical operating circuit interrupt to c vcc dxp1 dxn dxp2 reset gnd 2200pf 2200pf 2n3904 2n3904 10k each smbclk smbdata th_shut smbclk smbdata alert 0.1f reset p 0.1f vcc interrupt to c vcc dxp1 dxn dxp2 reset gnd 2200pf 2200pf 2n3904 2n3904 10k each smbclk smbdata th_shut smbclk smbdata alert 0.1f ss8017 reset p 0.1f vcc ss8017 re v . 2.01 6/06 /200 3
www.siliconstandard.com 3 of 16 ss8017 absolute maximum ratings vcc to gnd????.?.? ????????????????? .. ???. - 0.3v to +6v dxp to gnd???.??? ????????????????? .. ??..? - 0.3v to vcc + 0.3v dxn to gnd??? ???????????????? . ??..?????.. - 0.3v to +0.8v smbclk, smbdata, alert to gnd ?????????????? ... ? - 0.3v to +6v smbdata, alert current?? ???????????????? .. ??. - 1ma to +50ma dxn cu r rent??????? ??????????? .. ?..???????.1ma esd protection (smbclk, smbdata, alert , human body model).? ?.2000v esd protection (other pins, human bod y model) ???????????? .2000v continuous power dissip ation (t a = +70c) ??????????? .sop (de r ate 8.30mw/c above +70c)???? ???????????? .. .....667mw operating temperature range ??????????????????? - 2 0c to +120c junction temper a ture ??????????????????? . ???. .+150c storage temperature range ?????????????????? ??. - 65c to +165c lead temperature (soldering, 10sec)?? ???????????? ..??...+300c electrical characteristics (vcc = + 3.3v, t a = 0c to +85c, unless otherwise noted.) parameter conditions min typ m ax units t r = +60c to +100c, vcc = 3.0v to 3.6v - 1 +1 temperature error, remote d i- ode (note 1) t r = 0c to +125c (note 2) - 3 +3 c t a = +60c to +100c - 3 +3 temperature error, local diode t a = 0c to +85c (note 2) - 5 +5 c supply - voltage range 3.0 5.5 v undervoltage lockout threshold vcc input, disables a/d conversion, rising edge 2.8 v undervoltage lockout hysteresis 50 mv powe r - on reset t h reshold vcc, falling edge 1.7 v por threshold hysteresis 50 mv smbus static 3 standby supply cu r rent logic inputs forced t o vcc or gnd hardware or software standby, smbclk at 10khz 4 a 0.5 conv/sec 35 average operating supply current aut o - convert mode. logic inputs forced to vcc or g n d 8.0 conv/sec 320 a conversion time from stop bit to conversion complete (both channels) 125 ms conversion rate timing conversion - rate control byte=04h, 1hz 1 sec high level 176 remot e - diode source current dxp forced to 1.5v low level 11 a re v . 2.01 6/06 /200 3
www.siliconstandard.com 4 of 16 ss8017 electrical characteristics (cont.) re v . 2.01 6/06 /200 3 smbus interface logic input high voltage smbclk, smbdata; vcc = 4.5v to 5.5v 2.4 v logic input low voltage smbclk, smbdata; vcc = 4.5v to 5.5v 0.8 v logic output low sink current , smbdata forced to 0.4v 6 ma output high leakage current forced to 5.5v 1 a logic input current logic inputs forced to vcc or gnd -2 2 a smbus input capacitance smbclk, smbdata 5 pf smbus clock frequency (note 4) dc 100 khz smbclk clock low time t low , 10% to 10% points 4.7 s smbclk clock high time t high , 90% to 90% points 4 s smbus start-condition setup time 4.7 s smbus repeated start-condition setup time t su : sta , 90% to 90% points 500 ns smbus start-condition hold time t hd: sta , 10% of smbdata to 90% of smbclk 4 s smbus start-condition setup time t sd: sto , 90% of smbdata to 10% of smbdata 4 s smbus data valid to smbclk rising-edge time t su: dat , 10% or 90% of smbdata to 10% of smbclk 800 ns smbus data-hold time t hd : dat (note 5) 0 s smbclk falling edge to smbus data- valid time master clocking in data 1 s (v cc =full range, t a = 60c, unless otherwise noted.) parameter symbol conditions min typ max units reset threshold v th 4.2 4.4 4.5 v reset active timeout period 340 ms output voltage low v ol v cc =v th min i sink =3.2ma 0.4 v reset output voltage high v oh v cc >v th max, i source =5.0ma v cc -1.5 v note 1: guaranteed but not 100% tested. note 2: quantization error is not included in specifications for temperature accuracy. for example if the ss8017 device temperature is exactly +66.7c, or +68c (due to the quantization error plus the +1/2c offset used for rounding up) and still be within the guaranteed 3c error limits for the +60c to +100c tem- perature range. see table3. note 3: a remote diode is any diode-connected transistor from table1. t r is the junction temperature of the remote diode. see remote diode selection for remote diode forward voltage requirements. note 4: the smbus logic block is a static design that works with clock frequencies down to dc. while slow operation is possible, it violates the 10k hz minimum clock frequency and smbus specifications, and may monopolize the bus. note 5: note that a transition must internally provide at least a hold time in order to bridge the undefined region (300ns max) of smbclk's falling edge. (vcc = + 3.3v, t a = 0c to +85c, unless otherwise noted.) parameter conditions min typ max units
www.siliconstandard.com 5 of 16 1 2 3 4 5 6 7 8 nc vcc dxp1 dxn dxp2 dgnd agnd 16 15 14 13 12 11 10 9 smbclk nc alert nc reset ssop - 16l nc th_shut(push- pull) nc smbdata 1 2 3 4 5 6 7 8 nc vcc dxp1 dxn dxp2 dgnd agnd 16 15 14 13 12 11 10 9 smbclk nc alert nc reset ssop - 16l nc pin configuration th_shut(push- pull) nc smbdata pin name function 1,6,10,13,15 nc not connected. 2 vcc supply voltage input, 4.5v to 5.5v. bypass to gnd with a 0.1f c apacitor. 3 dxp1 combined current source and a/d positive input for remote- diode channel 1. do not leave dxp1 floating; tie dxp1 to dxn if no remote diode on channel 1 is used. place a 2200pf capacitor b e tween dxp1 and dxn for noise filtering. 4 dxn combined current sink and a/d negative input. dxn is common negative node of both remote d i odes on channel 1 and 2. the traces of dxp1 -dxn and dxp2 -dxn pairs should be routed inde pendently. the co m mon dxn should be connected together as close as possible to the ic. dxn is internally co n nected to the gnd pin for signal ground use. 5 dxp2 combined current source and a/d positive input for remote- diode channel 2. do not leave dxp2 floating; tie dxp2 to dxn if no remote diode on channel 2 is used. place a 2200pf capacitor b e tween dxp2 and dxn for noise filtering. 7 d gnd digital ground. 8 agnd analog ground. 9 reset reset output remains low while v cc is below the reset threshold, and for 240ms after v cc rises above the reset threshold. 11 alert smbus alert (interrupt) output, open drain. 12 smbdata smbus serial-data input / output, open drain. 14 smbclk smbus serial-clock input. 16 th_shut thermal shutdown output, push -pull output. pin description ss8017 re v . 2.01 6/06 /200 3
www.siliconstandard.com 6 of 16 block diagram thermal shutdown logic control logic smbus registers mux adc reset circuit th_shut smbclk smbdata alert reset v cc + + dxp1 dxn + internal ground v cc dxp2 thermal shutdown logic control logic smbus registers mux adc reset circuit th_shut smbclk smbdata alert reset v cc + + dxp1 dxn + internal ground the ss8017 consists of two temperature sensors, one on-chip temperature sensor and includes a system-reset function. the temperature sensor is designed to work in co n- junction with an external micro-controller ( c) or other inte lligence in thermostatic, process-control, or moni- toring applications. the c is typically a powerman- agement or keyboard controller, generating smbus serial commands by " bit-banging" general-purpose in- put -output (gpio) pins or via a dedicated smbus in- te rface block. essentially a 12-bit serial analog-to -digital converter (adc) with a sophisticated front end, the ss8017 con- tains a switched current source, a multiplexer, an adc, an smbus interface, a reset circuit and associated c ontrol logic (see block diagram above). temperature data from the adc is loaded into two data registers, where it is automatically compared with data previously stored in four over/under-temperature alarm registers. adc and multiplexer the adc is an averaging type that integrates over a 60ms period (each channel, typical). the multiplexer automatically steers bias currents through t wo remote diodes, measures their forward voltages, and computes their temperatures. all chan- nels are converted automatically once the conversion process has started, either in free-running or sin- gle-shot mode. if one of the two channels is not used, the device still performs all measurements, and the user can simply ignore the results of the unused chan- nel. if the remote diode channel is unused, tie dxpx to dxn rather than leaving the pins open. the dxn input is internally connected to the ground node inside the chip to set up the analog to digital (a/d) inputs for a differential measurement. the worst-case dxp -dxn differential input voltage range is 0.25v to 0.95v. excess resistance in series with the remote diode causes about +1/2 c error per ohm. likewise, 200v of offset voltage forced on dxp -dxn causes about 1 c error. detailed description ss8017 re v . 2.01 6/06 /200 3
www.siliconstandard.com 7 of 16 a/d conversion sequence if a start command is written (or generated automat i- cally in the free - running auto - convert mode), both two cha n nels are converted, and the results of both mea s- ur e ments are available after the end of conve r sion. a busy s tatus bit in the status byte shows that the d e- vice is a c tually performing a new conversion; however, even if the adc is busy, the results of the previous conversion are always available. remote - diode selection temperature accuracy depends on having a good - quality, diode - connected small - signal transistor. acc u racy has been experimentally verified for all of the devices listed in table 1. the 8017 can also directly measure the die temperature of cpus and other int e- grated circuits having on - board temper a ture - sensing diodes. the transistor must be a small - signal type with a relatively high forward voltage; otherwise, the a/d input voltage range can be violated. the forward vol t age must be greater than 0.25v at 10 a; check to ensure this is true at the highest e x pected temperature. the forward voltage must be less than 0.95v at 200a; check to e n sure this is true at the lo w est expected temperature. large power transistors don't work at all. also, ensure that the base resistance is less than 1 00 w . tight spec i ficati ons for forward current gain (+50 to +150, for example) indicate that the manufacturer has good process controls and that the devices have consistent vbe cha r acteristics. thermal mass and self - heating thermal mass can seriously degrade the 8017's effec- tiv e accuracy. the thermal time constant of the ssop - 16 package is about 140sec in still air. for the 8017 junction temperature to settle to within +1c after a sudden +100 c change requires about five time co n- stants or 12 minutes. the use of smaller packages for remote sensors, such as sot23s, improves the situ a- tion. take care to account for thermal gradients b e- tween the heat source and the se n sor ,and ensure that stray air current across the sensor package does not interfere with measurement acc u racy. table 1. remote - sensor transistor manufacturers manufacturer model number philips pmbs 3904 motorola (usa) mmbt3904 national semicondu c tor (usa) mmbt3904 note:transistors must be diode - connected (base short - ed to collector). adc noise filtering the adc is an integrating type with inherently good noise rejection, especially of low - frequency signals such as 60hz/120hz power - supply hum. micro - power oper a tion places constraints on high - frequency noise rejection; therefore, careful pc board layout and proper extern al noise filtering are required for high - accuracy remote measurements in electrically noisy enviro n- ments. high - frequency emi is best filtered at dxp and dxn with an external 2200pf capacitor. this value can be increased to about 3300pf(max), including cab le c a- pacitance. higher capacitance than 3300pf introduces errors due to the rise time of the switched current source. nearly all noise sources tested cause the adc mea s- urements to be higher than the actual temperature, typically by +1 c to 10 c , depending on the frequency and amplitude (see typical operating chara c teristics). pc board layout place the 8017 as close as practical to the remote diode. in a noisy environment, such as a computer mothe r board, this distance can be 4 in. to 8 in. (typical) or more as long as the worst noise sources (such as crts, clock generators, memory buses, and isa/pci buses) are avoided. do not route the dxp - dxn lines next to the deflection coils of a crt. also, do not route the traces across a fast memory bus, which can easily introduce +30 c error, even with good filtering, otherwise, most noise sources are fairly benign. route the dxp and dxn traces in parallel and in close proximity to each other, away from any high - voltage traces such as +12vdc. leakage currents from pc boa rd contamination must be dealt with carefully, since a 20m w leakage path from dxp to ground causes about +1 c error. route the 2 pairs of dxp1 - dxn and dxp2 - dxn traces independently (figure 2a). connect the co m mon dxn as close as possible to the dxn pin on ic (figure 2a). connect guard traces to gnd on either side of the dxp - dxn traces (figure 2 b ). with guard traces in place, routing near high - voltage traces is no longer an issue. route through as few vias and crossunders as poss i ble to minimize copper/solde r the r mocouple effects. when introducing a thermocouple, make sure that both the dxp and the dxn paths have matching thermoco u- ples. in general, pc board - induced the r mocouples are not a serious problem, a copper - solder therm o couple exhibits 3 v/c, and it takes about 200v of voltage error at dxp - dxn to cause a +1 c measur e ment error. ss8017 re v . 2.01 6/06 /200 3
www.siliconstandard.com 8 of 16 in this way, most parasitic thermocouple errors are swamped out. use wide traces. narrow ones are more inductive and tend to pick up radiated noise. the 10 mil widths and spacing recom mended on figure 2 aren't absolutely ne c essary (as they offer only a minor improvement in leakage and noise), but try to use them where pract i- cal. keep in mind that copper can't be used as an emi shield, and only ferrous materials such as steelwork will. p la c ing a copper ground plane between the dxp - dxn traces and traces carrying high - frequency noise signals do not help reduce emi. pc board layout checklist n place the 8017 close to a remote diode. n keep traces away from high voltages (+12v bus). n keep traces away from fast data buses and crts. n use recommended trace widths and spacing. n place a ground plane under the traces n use guard traces flanking dxp and dxn and co n- necting to gnd. n route two dxpx - dxn pairs indepen d ently n connect the common dxn as close as possi ble to the dxn pin on ic. n place the noise filter and the 0.1 f vcc bypass capacitors close to the 8017. fig 2(a) connect the common dxn as close as po s sible to the dxn pin on ic. twisted pair and shielded cables for remote-sensor distances longer than 8 in., or in pa r ticularly noisy environments, a twisted pair is re c- o m mended. its practical length is 6 feet to 12 feet (typi- cal) before noise becomes a problem, as tested in a noisy electronics laboratory. for longer dista nces, the best solution is a shielded twisted pair like that used for audio microphones. connect the twisted pair to dxp and dxn and the shield to gnd, and leave the shield's remote end u n terminated. excess capacitance at dx_ limits practical remote sen- sor distances (see typical operating characteri s tics), for very long cable runs, the cable's parasitic capac i- tance often provides noise filtering, so the 2200pf c a- pacitor can often be removed or reduced in value. c a- ble resistance also affects remote - sensor acc uracy; 1 w s e ries resistance introduces about + 1 c error. low - power standby mode standby mode disables the adc and reduces the su p- ply - current drain to less than 10 a. enter standby mode via the run/stop bit in the configuration byte register. in standby m ode, all data is retained in me m- ory, and the smb interface is alive and listening for reads and writes. this is valid for temperature sensor only. standby mode is not a shutdown mode. with activity on the smbus, extra supply current is drawn (see typ i cal o perating characteristics). in software standby mode, the 8017 can be forced to perform temperature mea s urement via the one - shot command, despite the run/stop bit b e ing high. supply - current drain during the 125ms conversion pe- riod is always about 500 a. slo wing down the conve r- sion rate reduces the average supply current (see typ i cal operating characteristics). in between co n ve r- sions, the instantaneous supply current is about 2 00 a due to the current consumed by the system resetting circuit. reset immunity ne gative - going v cc tra n sients in addition to issuing a reset to the microprocessor ( p) during power - up, power - down, and brownout cond i tions, the 8017 is relatively immune to short duration nega- tive - going v cc transients (glitches). typically, for the 8017, a v cc transient that goes 100mv below the reset threshold and lasts 20 s or less will not cause a reset pulse. a 0.1 f bypass c a- pacitor mounted as close as possible to the v cc pin provides additional transient immunity. dxp1 dxn dxn dxp2 dxp1 dxn dxp2 gnd chip boundary gnd dxp1 dxn dxn dxp2 dxp1 dxn ss8017 dxp2 gnd chip boundary gnd gnd dxp dxn gnd 10 mils minimum 10 mils 10 mils 10 mils gnd gnd dxp dxp dxn dxn gnd gnd 10 mils minimum 10 mils 10 mils 10 mils fig 2 (b) recommended dxp/dxn pc ss8017 re v . 2.01 6/06 /200 3
www.siliconstandard.com 9 of 16 ss8017 re v . 2.01 6/06 /200 3 ensuring a valid reset output down to v cc = 0v when v cc falls below 1v, the ss8017 reset out- put no longer sinks current -it becomes an open cir- cuit. therefore, high-impedance cmos logic inputs co nnected to reset can drift to undetermined volt- ages. this presents no problem in most applications, since most p and other circuitry is inoperative with v cc below 1v. however, in applications where reset must be valid down to 0v, adding a pull-down resistor to reset causes any stray leakage currents to flow to ground, holding reset low (figure 3). r1's value is not critical; 100k w is large enough not to load reset and small enough to pull reset to ground. interfacing to ps with bi -directional reset pins a p with bi-directional reset pins (such as the m o- torola 68hc11 series) can connect to the ss8017 reset output. if, for example, the ss8017 reset output is a sserted high and the p wants to pull it low, indete rminate logic levels may result. to correct this, co nnect a 4.7 kw resistor b etween the ss8017 reset output and the p reset i/o (figure 4). buffer the ss8017 reset output to other sys- tem components. benefits of highly accurate reset thres hold most p supervisor ics have reset threshold voltages between 5% and 10% below the value of nominal su pply voltages. this ensures a reset will not occur within 5% of the nominal supply, but will occur when the su pply is 10% below nominal. when using i cs rated at only the n ominal supply 5% this leaves a zone of uncertainty where the su p- ply is b etween 5% and 10% low, and where the reset may or may not be asserted. the ss8017 uses highly accurate circuitry to en- sure that reset is asserted close to the 5% limit, and long b e fore the supply has declined to 10% below nominal. smbus digital interface from a software perspective, the ss8017 appears as a set of byte -wide registers that contain temperature data, alarm threshold values, fan speed data, or co n- trol bits, a standard smbus 2 -wire serial interface is used to read temperature data and write control bits and alarm threshold data. each a/d and fan control channel within the device responds to the same smbus slave address for normal reads and writes. the ss8017 employs four standard smbus protocols: write byte, read byte, send byte, and receive byte (figure 5). the shorter receive byte protocol allows quicker transfers, provided that the correct data register was previously selected by a read byte instruction. use caution with the shorter protocols in multi-master systems, since a second master could over-write the command byte without informing the first master. the temperature data format is 7bits plus sign in twos -complement form for each channel, with each data bit representing 1 c (table3), transmitted msb first. measurements are offset by +1/2 c to minimize internal rounding errors; for example, +99.6 c is r e- ported as +100c. fig 4. interfacing to ps with bi -directional reset i/o fig 3. reset valid to v cc = ground circuit v cc reset gnd r1 100k v cc ss8017 reset gnd r1 100k v cc reset gnd buffer reset gnd v cc p 4.7 k buffered reset to other system components v cc ss8017 reset gnd buffer reset gnd v cc p 4.7 k buffered reset to other system components
www.siliconstandard.com 10 of 16 ss8017 re v . 2.01 6/06 /200 3 w rite byte format s address wr ack co m mand ack data ack p 7 bits 8 bits 8 bits 1 slave address: equivalent to chip - select line of a 3 - wire interface command byte: selects , which register you , are writing to data byte: data goes into the register s et by the command byte (to set thresholds, co n figuration masks, and sampling rate) read byte format s address wr ack co m mand ack s address rd ack data /// p 7 bits 8 bits 7 bits 8 bits slave address: equivalent to chip - select line command byte: selects , which register you , are reading from slave address: repeated due to change in data - flow direction data byte: reads from the register set by the command byte send byte format s address wr ack command ack p 7 bits 8 bits command byte: sends command with no data usually used for one - shot command receive byte format s address rd ack data /// p 7 bits 8 bits data byte: reads data from the register co m manded by the last read byte or write byte transmission ; also use d for smbus alert response return address s = start condition shaded = slave transmission p = stop condition /// = not a c knowledged fig 5. smbus protocols
www.siliconstandard.com 11 of 16 ss8017 re v . 2.01 6/06 /200 3 table 3. data format (twos -complement) digital output data bits temp. ( c) round temp. ( c) sign msb lsb +130.00 +127 0 111 1111 +127.00 +127 0 111 1111 +126.50 +127 0 111 1111 +126.00 +126 0 111 1110 +25.25 +25 0 001 1001 +0.50 +1 0 000 0001 +0.25 +0 0 000 0000 +0.00 +0 0 000 0000 -0.25 +0 0 000 0000 -0.50 +0 0 000 0000 -0.75 -1 1 111 1111 -1.00 -1 1 111 1111 -25.00 -25 1 110 0111 -25.50 -25 1 110 0110 -54.75 -55 1 100 1001 -55.00 -55 1 100 1001 -65.00 -65 1 011 1111 -70.00 -65 1 011 1111 alarm threshold registers four registers store alarm threshold data, with high-temperature (thigh) and low-temperature (tlow) registers for each a/d channel. if either measured te m- perature equals or exceeds the corresponding alarm threshold value, an alert interrupt is a sserted. the power-on-reset (por) state of both thigh regis- ters is full scale (0111 1111, or +127c). the por state of both tlow registers is 1100 1001 or -55c. diode fault alarm there is a continuity fault detector at dxp that detects whether the remote diode has an open-circuit condition. at the beginning of each conversion, the diode fault is checked, and the status byte is updated. this fault detector is a simple voltage detector; if dxp rises abo- ve v cc - 1v (typical) due to the diode current source, a fault is detected. note that the diode fault isn't checked until a conversion is initiated, so immediately after power-on reset the status byte indicates no fault is present, even if the diode path is broken. if the remote channel is shorted (dxp to dxn or dxp to gnd), the adc reads 0000 0000 so as not t o trip e i- ther the thigh or tlow alarms at their por se ttings. in applications that are never subjected to 0 c in nor- mal operation, a 0000 0000 result can be checked to indicate a fault condition in which dxp is accidentally short circuited. similarly, if d xp is short circuited to v cc , the adc reads +127c for both channels, and the device alarms. alert interrupts the alert interrupt output signal is latched and can only be cleared by reading the alert response a ddress. inte rrupts are generated in response to thigh and tlow comparisons and when the remote diode is dis- connected (for continuity fault detection). the i nte rrupt does not halt automatic conversions; new te mperature data continues to be available over the smbus inte r- face after alert is asserted. the inte rrupt output pin is open-drain so that device can share a common i n- terrupt line. the interrupt rate can never exceed the conve rsion rate. the interface responds to the smbus alert response address, an interrupt pointer return-address feature (see alert response address section). prior to taking corrective action, always check to ensure that an i n- te rrupt is valid by reading the current temperature. alert response address the smbus alert response interrupt pointer provides quick fault identification for simple slave devices that lack the complex, expensive logic needed to be a bus master. upon receiving an alert interrupt signal, the host master can broadcast a receive byte transmis- sion t o the alert response slave address (0001 100). then any slave device that generated an interrupt a t- tempts to identify itself by putting its own address on the bus.
www.siliconstandard.com 12 of 16 ss8017 re v . 2.01 6/06 /200 3 table 4. command - byte bit assignments register command p or state function rrte2 00h 0000 0 000 b read 2nd remote temperature: returns latest te m perature rrte1 01h 0000 0000 b read 1st remote temperature: returns latest te m perature rsl 02h n/a read status byte (flags, busy signal) rcl 03h 0000 0000 b read configuration byte rcra 04h 0000 0010 b r ead conversion rate byte rrhi2 05h 0111 1111 b (127) read 2nd remote thigh limit rrls2 06h 1100 1001 b( - 55) read 2nd remote tlow limit rrhi1 07h 0111 1111 b (127) read 1st remote thigh limit rrls1 08h 1100 1001 b ( - 55) read 1st remote tlow limit wca 09h n /a write configuration byte wcrw 0ah n/a write conversion rate byte wrha2 0bh n/a write 2nd remote thigh limit wrln2 0ch n/a write 2nd remote tlow limit wrha1 0dh n/a write 1st remote thigh limit wrln1 0eh n/a write 1st remote tlow limit osht 0fh n/a one - shot command (use send - byte format) tcrit1 35h 0110 1100b (108) critical temperature for 1 st remote temperaure sensor tcrit2 36h 0101 1000b (88) critical temperature for 2 nd remote temperaure sensor the alert response can activate several differe nt slave devices simultaneously, similar to the smbus general call. if more than one slave attempts to respond, bus arbitration rules apply, and the device with the lower a d dress code wins. the losing device does not generate a n acknowledge and continues to hold the alert line low until serviced (implies that the host i n terrupt input is level sensitive). successful reading of the alert response address clears the inte r- rupt latch. command byte functions the 8 - bit command byte register (tabl e 4) is the ma s- ter index that points to the various other registers within the ss8017 . the register's por state is 0000 0000, so that a receive byte transmission (a protocol that lacks the co m mand byte) that occurs immediately after por r e turns the current l ocal te m perature data. the one - shot command immediately forces a new co n- version cycle to begin. in software standby mode ( run /stop bit = high), a new conversion is begun, a f ter which the device returns to standby mode. if a co n version i s in progress when a one - shot command is r e ceived in auto - convert mode (run/stop bit = low) b e tween conversions, a new co n version begins, the co n version rate timer is reset, and the next automatic co n version takes place after a full delay elapses. configu ration byte functions the configuration byte register contents are listed in table 5. bit 7 (mask) is used to mask alert inte r- rupt. bit 6 ( run /stop ) is to put the device in sof t ware standby mode. setting bit 5 (det_fan) with logic 1 can activate the d e tection of fan failure. logic 1 in bit 4 (en_th_shut) makes thermal shutdown function valid and logic 0 disables this function and keep th_shut pin low. bit 3~0 forms thermal shu t down fault queue. the number of faults these bits d e cided are listed in table 6. thermal status byte functions the thermal status byte register (02h) (table 6) ind i- cates which (if any) temperature thresholds have been e x ceeded. this byte also indicates whether or not the adc is converting and whethe r there is an open circuit in the remote diode dxpx - dxn path. after por, the normal state of all the flag bits is zero, assuming none of the alarm conditions are present. the status byte is cleared by any successful read of the status, unless the fault pe r sists. note that the alert interrupt latch is not aut o matically cleared when the status flag bit is cleared. when reading the status byte, you must check for i n- te r nal bus collisions caused by asynchronous adc timing, or else disable the ad c prior to reading the status byte (via the run /stop bit in the configur a tion byte). in one - shot mode, read the status byte only a f ter the co n version is complete, which is 150ms max after the one-shot conversion is commanded.
www.siliconstandard.com 13 of 16 ss8017 re v . 2.01 6/06 /200 3 table 5. configuration-byte bit assignments bit name por state function 7 (msb) mask 0 masks all alert interrupts when high. 6 run / stop 0 standby mode control bit. if high, the device immediately stops converting and enters standby mode. if low, the device converts in either one-shot or timer mode. 5 det_fan 0 should be 0. changing this to 1 will cause alert function abnormal. 4 en_th_shut 1 validation of the fault queue function of thermal shutdown. 3-0 fq_th_shut 0010b fault queue. number of faults necessary to detect before setting th_shut output to avoid false tripping due to noise. table 6. number of faults assigned by fq_th_shut fq_th_shut number of faults fq_th_shut number of faults 0000b 1 1000b 9 0001b 2 1001b 10 0010b 3(power-up default) 1010b 11 0011b 4 1011b 12 0100b 5 1100b 13 0101b 6 1101b 14 0110b 7 1110b 15 0111b 8 1111b 16 table 7. status -byte bit assignments bit name function 7(msb) busy a high indicates that the adc is busy converting. 6 rhigh2* a high indicates that the 2 nd diode high-temperature alarm has act ivated. 5 rlow2* a high indicates that the 2 nd diode low -temperature alarm has activated. 4 rhigh1* a high indicates that the 1 st diode high-temperature alarm has act ivated. 3 rlow1* a high indicates that the 1 st diode low -temperature alarm has activated. 2 open* a high indicates a remote-diode continuity (open-circuit) fault. 1 rfu reserved for future use (returns 0) 0(lsb) rfu reserved for future use (returns 0) *these flags stay high until cleared by por, or until the status byte register is read. table 8. conversion-rate control byte data conversion rate (hz) temperature sensor average supply current ( a typ, at vcc = 5v) 00h 0.0625 30 01h 0.125 33 02h 0.25 35 03h 0.5 48 04h 1 70 05h 2 128 06h 4 225 07h 8 425 08h to ffh rfu -
www.siliconstandard.com 14 of 16 ss8017 re v . 2.01 6/06 /200 3 table 9. rlts and rrte temp register update timing chart operating mode conversion initiated by: new c onversion r ate (changed via write to crw) time until rlts and rrte are updated auto-convert power-on reset n/a (0.25hz) 156ms max auto-convert 1-shot command, while idling be- tween automatic conve rsions n/a 156ms max auto-convert 1-shot command that occurs dur- ing a conversion n/a when current conversion is complete (1-shot is ignored) auto-convert rate timer 0.0625hz 20sec auto-convert rate timer 0.125hz 10sec auto-convert rate timer 0.25hz 5sec auto-convert rate timer 0.5hz 2.5sec auto-convert rate timer 1hz 1.25sec auto-convert rate timer 2hz 625ms auto-convert rate timer 4hz 312.5ms auto-convert rate timer 8hz 237.5ms software standby run/stop bit n/a 156ms software standby 1-shot command n/a 156ms to check for internal bus collisions, read the status byte. if the least significant seven bits are ones, dis- card the data and read the status byte again. the status bits lhigh, llow, rhigh, and rlow are r e- freshed on the smbus clock edge immediately follow- ing the stop condition, so there is no danger of losing temperature-related status data as a result of an inte r- nal bus collision. the open status bit (diode continu- ity fault) is only refreshed at the beginning of a conve r- sion, so open data is lost. the alert interrupt latch is independent of the status byte register, so no false alerts are generated by an internal bus collision. when auto -converting, if the thigh and tlow limits are close together, it's possible for both high-te mp and low-temp status bits to be set, depending on the amount of time between status read operations (esp e- cially when converting at the fastest rate). in these cir- cumstances, it's best not to rely on the status bits to indicate reversals in long-term temperature changes and instead use a current temperature reading to e s- tablish the trend direction. temperature conversion rate byte the conversion rate register (table 7) programs the time interval between conversions in free running auto -convert mode. this v ariable rate control reduces the supply cu rrent in portable-equipment applications. the conversion rate byte's por state is 02h (0.25hz). t he ss8017 looks only at the 3 lsb bits of this regis- ter, so the upper 5 bits are "don't care" bits, which should be set to zero. the conversion rate tolerance is 25% at any rate se tting. valid a/d conversion results for all channels are avail- able one total conversion time (125ms nominal, 156ms maximum) after initiating a conversion, whether co n- ve rsion is initiated via t he run/stop bit, one-shot co mmand, or initial power-up. changing the conve rsion rate can also affect the delay until new results are available. see t able 8. slave addresses the ss8017 appears to the smbus as one device hav- ing a common address for all the adc and fan control channels. the device address is fixed to be 7ah for write and 7bh for read. the ss8017 also responds to the smbus alert r e- sponse slave address (see the alert response a d- dress se ction). por and uvlo the ss8017 has a volatile memory. to p revent a m- biguous power-supply conditions from corrupting the data in memory and causing erratic behavior, a por voltage detector monitors vcc and clears the memory if vcc falls below 1.7v (typical, see electrical charac- teristics table). when power is first applied and vcc rises above 1.75v (typical), the logic blocks begin operating, a lthough reads and writes at v cc levels
though reads and writes at v cc levels below 3v are not recommended. a second vcc comparator, the adc uvlo comparator, prevents the adc from converting until there is sufficie nt headroom (vcc = 2.8v typ i cal). power - up defaults: n interrupt latch is cleared. n adc begins auto / converting at a 0.25hz rate. n command byte is set to 00h to facilitate quick r e- mote receive byte queries. n thigh and tlow registers are set to max and min lim its, respectively thermal shutdown signal when the temperature of dx1 reaches or exceeds the tcrit1 threshold consecutively for the times equal to the number of faults of the fq_th_shut regi s ters, th_shut pin becomes logic high. the same mech a- nism is d u pli cated for dx2. there fore, either one of dx1, dx2 continuously over their r e spective tcrit, the th_shut will assert logic high to i n dicate a thermal shutdown event. figure 6. smbus write timing di a gram a = start condition h = lsb of data clocked into s lave b = msb of address clocked into slave i = slave pulls smbdata line low c = lsb of address clocked into slave j = acknowledge clocked into master d = r / w bit clocked into slave k = acknowledge clocked pulse e = slave pulls smb data line low l = s top condition data executed by slave f = acknowledge bit clocked into master m = new start condition g = msb of data clocked into slave figure 7. smbus read timing diagram a = start condition g = msb of data clocked into master b = msb of address cl ocked into slave h = lsb of data clocked into master c = lsb of address clocked into slave i = acknowledge clocked pulse d = r / w bit clocked into slave j = stop condition e = slave pulls smbdata line low k= new start condition f =acknowledge bit clocked into master smbclk smbdata a b c d e f g h i j k l m t su :sta t hd :sta t su :dat t hd :dat t su :sto t buf t low t high smbclk smbdata a b c d e f g h i j k t su :sta t hd :sta t su :dat t su :sto t buf t low t high smbclk smbdata a b c d e f g h i j k t su :sta t hd :sta t su :dat t su :sto t buf t low t high www.siliconstandard.com 15 of 16 ss8017 re v . 2.01 6/06 /200 3
www.siliconstandard.com 16 of 16 ss8017 in formation furnished by silicon standard corporation is believe d to be accurate and reliable. however, silicon standard corporation makes no guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infri ngement of any patent or other intellectual property rights of third parties that may result from its use. silicon standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitat ion enhancement in reliability, functionality or design. no license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intelle ctual property rights of silicon standard corporation or any third parties. physical dimensions re v . 2.01 6/06 /200 3 re v . 2.01 6/06 /200 3 note: 1. package body sizes exclude mold flash and gate burrs 2. dimension l is measured in gage plane 3. tolerance 0.10mm unless other wise specified 4. controlling dimension is millimeter converted inch dimensions are not necessarily exact. dimension in mm dimension in inch symbols min nom max min nom max a 1.35 1.60 1.75 0.053 0.064 0.069 a1 0.10 ----- 0.25 0.004 ----- 0.010 a2 ----- 1.45 ----- ----- 0.057 ----- b 0.20 0.25 0.30 0.008 0.010 0.012 c 0.19 ----- 0.25 0.007 ----- 0.010 d 4.80 ----- 5.00 0.189 ----- 0.197 e 5.80 ----- 6.20 0.228 --- -- 0.244 e1 3.80 ----- 4.00 0.150 ----- 0.157 e ----- 0.64 ----- ----- 0.025 ----- l 0.40 ----- 1.27 0.016 ----- 0.050 y ----- ----- 0.10 ----- ----- 0.004 ? 0o ----- 8o 0o ----- 8o d e1 e 7 x (4 x) a1 a2 a e b y c l q t aping specification feed direction typical ssop package orientation feed direction typical ssop package orientation

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